HCL America Hiring: Validation FPGA Design Engineer - San Jose, CA

Qualifications:

- BSEE required, MSEE preferred

- A minimum of 2 years' experience in a SOC Validation or Field Applications Engineering role.

- Familiarity with pre-silicon and post-silicon validation environment, debugging, preparation of validation test reports and chip bug reports

- Experience with typical lab equipment such as logic analyzers, oscilloscopes, in-circuit emulators, etc.

- Knowledge of system I/O protocols such as SATA, SCSI, or SAS.

- Experience with C, assembly and or low level hardware coding (setting bits and writing bytes to initialize and configure ASICs for test operations).

- Familiar with memory systems such as FLASH/ONFI

- Ability to read and use Verilog hardware models for detailed investigations of ASIC issues and test verification/debug.

Description:

- Responsible for silicon validation and generation of appropriate test reports.

- Work closely with design engineers to insure all critical test points.

Thanks,

Jayan Chhaya

Ph: +1-860-967-0219

Mail: jayan.c@hcl.com